`timescale 1ns / 1ps

module fifo_testbench;

reg clk_tb;
reg rst_n_tb;

wire clk_100M_tb;
wire clk_75M_tb;
wire locked_tb;
wire fifo_rst_n_tb;
wire wr_clk_tb;
wire rd_clk_tb;
wire wr_en_tb;
wire rd_en_tb;
wire full_tb;
wire empty_tb;
wire [15:0] r_data_tb;
wire [8:0] rd_data_count_tb;
wire [8:0] wr_data_count_tb;

fifo_test uut (
    .clk(clk_tb),
    .rst_n(rst_n_tb),
    .clk_100M(clk_100M_tb),
    .clk_75M(clk_75M_tb),
    .locked(locked_tb),
    .fifo_rst_n(fifo_rst_n_tb),
    .wr_clk(wr_clk_tb),
    .rd_clk(rd_clk_tb),
    .wr_en(wr_en_tb),
    .rd_en(rd_en_tb),
    .full(full_tb),
    .empty(empty_tb),
    .r_data(r_data_tb),
    .rd_data_count(rd_data_count_tb),
    .wr_data_count(wr_data_count_tb)
);


initial begin
    clk_tb = 0;
    forever #10 clk_tb = ~clk_tb;
end


initial begin

    rst_n_tb = 0;

    rst_n_tb = 1;

    wait(locked_tb);


    #1000;
    $finish;
end

initial begin
    $monitor("Time=%t, wr_en=%b, rd_en=%b, full=%b, empty=%b, r_data=%h, rd_data_count=%d, wr_data_count=%d",
             $time, wr_en_tb, rd_en_tb, full_tb, empty_tb, r_data_tb, rd_data_count_tb, wr_data_count_tb);
end



endmodule
